June 17, 2020 0 Comments

1 BCM datasheet errata. the BCM Broadcom specifies the reserved bits the other way around: “Write zeroes, read: don’t care”. Read about ‘Broadcom: Datasheet for BCM ARM Peripherals’ on element14 .com. Broadcom: Datasheet for BCM ARM Peripherals. If you have been following Raspberry Pi project, you may have noticed the dearth of documentation related to Broadcom processors.

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The partial datasheet was dataheet here: The quality of the datasheet is high. It looks like it contains the information that programmers need. Some of the tables from the datasheet have been reproduced here. It also “does the right thing” with reserved bits. Many datasheets specify “write: Broadcom specifies the reserved bits the other way around: This is the correct way to do it. If you expand the hardware the hardware may be enhanced and do “different things” if you write ones to the previously “reserved” bits.

If you follow the datasheet, and write zeroes as specified to the reserved bits, the hardware guys can make sure dahasheet not going to run into surprises. And by specifying “read: Not really an erratum, but not worth it to make a whole page for this. The I2C dwtasheet on page 34 mentions MHz as a “nominal core clock”. Switch on option for linking, so cross-references and table of contents can be jumped through. The “description” is then SPI This datasheeet confusing as indeed there is a different module called SPI0 documented on page and onwards.

They should both read “If this bit cleared no new symbols will be The register reads as 0x after reset. Two bits dataseet would be consistent with TX empty and RX empty. However, bits 7 and 9 does not match the original datasheet, nor my guess The Peek register is documented here as being at 0x7ec, whereas the table on page 8 shows 0x7e The IO register is documented as 0x7ea0 with automatic broadclm and 0x7eb0, whereas the table on page 8 shows 0x7e I strongly suspect that the CDIV counter is only 14 bits wide.


BCM Datasheet(PDF) – Broadcom Corporation.

The bottom bit doesn’t work as per specifications, and because the “0” results inthe top bit doesn’t either. An easy implementation would implement the 0 value as the maximum divisor. Not as “half the maximum”. There is a bug in the I2C master that it does not support clock stretching at arbitrary points. A detailed analysis of this bug can be found at http: Link to it via two control blocks on the primary chain.

This shows a bit pattern of as alternative function 3. This does not match the diagram on page – which shows this function is selected with alternative function 4. Instead of “when all register contents is lost. The table, legend for tablestarted on page shows twice in red: The second block, with functions starting: UART 1 should be: In table the values in columns “min output freq” and “max output freq” should be in each others.

That is the values in column “min output freq” are the maximum output frequency values and the values in column “max output freq” are the minimum output frequency values [check: Introduction This test application is intended to present a bcm285 to understand user space test application that can be used to control the output of the Raspberry PI I2S bus. This dayasheet lead to a confusing picture.

Therefore, the aim of this small test application project is to:. This is from Geert Van Loos at the page below:.

I assume you want the cleanest clock source which is the XTAL The divider is split between an integer divider and a fractional mashing divider.

The mashing dividers are build such that clock artifacts should be pushed out of the audio frequency domain.

You must write the MS 8 bits as 0x5A. Allusions to the APB clock domain are made. However the exact speed of the APB clock is never bbcm2835. There is amiguity on what register bits can be modified while the I2S system is active. Does this mean, that the SYNC bit can also be changed at runtime as well?


I think- not confirmed. Near the bottom of the page RXR. This bit would be useful if it signified more than bcmm2835 full. There is a space in ” full ” that would hint at that the word “half” was taken away.

Another hint is that it says that the bit clears when “sufficient” data is read from the FIFO. The word sufficient is redundant when this is the “full and active” bit. The way it is written now, datasueet bit is just the same as bit RXF, except that the TA bit is anded into this one.

Datashfet hardware was changed detecting “half full” was difficult? Or the hardware does what I expect: How do these combine???

I dunno the official answer to this, but the community-written SPI drivers here and here set them both at the same time. This may happen every time this bit is set, but it is not measurable every time when sampling at 16MHz higher sampling speeds would be needed to confirm that. The CDIV value is documented as “must be a power of 2”.

BCM datasheet errata –

This is not true. Under rare situations this may result in “lost” clocks while MOSI still shifts out the data!

Possibly the “choice” hasn’t been specified. Retrieved from ” https: Navigation menu Personal tools Log in Request account. Views Read View source View history.

Raspberry Pi Releases BCM2835 Datasheet for ARM Peripherals

This page was last edited broaadcom 9 Julyat Privacy policy About eLinux. If 1 the data is shifted in starting with the MS bit. If 1 the receiver shift register is NOT cleared. Thus new data is concatenated to old data. If 0 the receiver shift register is cleared before each transaction.