CAPLESS LDO PDF
In this paper, a capless LDO regulator with a negative capacitance circuit (NCC) and voltage damper (VD) is proposed for enhancing PSR and figure-of-merit. Low dropout (LDO) voltage regulators are generally used to supply low voltage, Each LDO regulator demands a large external capacitor, in the range of a few. Initially, a theoretical macromodel is presented based on the analogy between the capless LDO and the mechanical non-linear harmonic oscillator, enabling to .
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Results 1 to 20 of Milliken’s capless LDO technique. Please correct me if I’m wrong.
One is at the LDO’s output, the other two are at the output of each stage of error amp. Assuming that the output cap is very small, which may be true since you said about capless LDO, we can say that the three poles location is quite near.
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In order to achieve stability, you need to: There are many techniques to push the pole to lower frequency. The most famous one is by using Miller compensation, which is based on pole splitting technique. The problem with this technique is the existence of RHP zero, which is unwanted. To eliminate this RHP zero, many method has been proposed, e. Some of these technique even can introduce LHP zero. One of the problem in LDO is due to its changing load resistance. In conventional LDO, people create a dominant pole using this changing load resistance and a very big output cap.
The problem occurs when RL is very small due to the heavy load current. At this time, the dominant pole shifts to higher frequency, causing the non-dominant poles to be located inside the UGF.
Milliken’s capless LDO technique
However, this technique requires a very big cap and specific range of ESR, which makes this compensation a bit troubelsome and not suitable for SoC. Nowadays, kdo very seldomly make use of the output pole as the dominant one. They usually create a dominant pole by using the enhanced Miller compensation, which has been discussed earlier.
To compensate the changing pole, some odo try to lower the UGF and use a constant zero to compensate it when it comes near the UGF. Other researchers proposed to use a dynamic zero, which is able to change its location according to the load current.
The problem with this technique is that, it cannot accurately track the load pole, because it is only dlo to track the load current, but not the load capacitance.
However, it is still much better than just a constant zero. For the dynamic zero, you can look at this paper: Hope it can help. Good thing about the design is that it works with the stated boundries. The problem occurs when you simulate caplesz for corner cases.
Typical case it works quite fine.
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Thanks for your inputs. Their transient load regulation spec will be tight. It will not suit for practical application. As I remembered, an external reference is used in his paper. For LDO product, internal reference should be must. The mismatching problem will be obvious. Does it mean it can work only without cap? I don’t think it will be the case since some pass caplesss will always be added to enhance the transient repsonse, say spike or dip, in such case, is it possible to develop a LDO that is adaptive to all cap?
Someone proposed to shift the dominant pole to the internal, but will that survive with any cap, especially at no load? Even that we can introduce a zero in internal circuit, how much space will it cost? Is this also the same for the nfet device design? Also assuming that the parasitic Cgs and Cgd can be handled properly, what is the minimum Vdropout that a real life design can cappess in today’s CMOS technology?
Capless LDO design- experience sharing and papers needed 1. Capless LDO design stability problem 3.
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